1. Field of the Invention
The present invention relates generally to a built-in self test (BIST) technique, and relates more particularly to a test pattern generator which does not fall into a self looping mode.
2. Technical Background
Digital integrated circuits are conventionally tested by successively applying test patterns to the inputs of the circuit. Upon receipt of each test pattern, which is composed of a plurality of ones and zeros, the circuit responds by producing a result at its outputs, each result also being composed of a pattern of ones and zeros. When the circuit is operating properly, the response at each output of the circuit will match an expected result for each input test pattern. If an fault exists, then a mismatch occurs. Usually, a set of test patterns is generated by a test pattern generator which is constructed in the same chip with a core circuit. When powering thereon, the test pattern generator (TPG) is triggered to generate a plurality of test patterns to the inputs of the core circuit, successively. This is a built-in self test (BIST) technique.
If a higher percentage of possible faults can be detected, there is a greater confidence in the lack of any faults in the circuit. However, achieving 100% fault coverage is typically very difficult without exhaustive testing. In the past, testing of a circuit has been accomplished by first mathematically modeling the circuit and all its possible faults. Using the mathematical model, a set of test patterns is then generated. While algorithms for fault simulation and test pattern generation exist, applying such algorithms to a circuit of even moderate complexity is a time-consuming task, often requiring weeks or months of effort. Thus, there is a need for a technique for achieving 100% fault coverage of a sequential digital integrated circuit without the need for fault simulation or deterministic test generation.
Conventional test pattern generator 100 is shown in FIG. 1, which exemplifies a typical 4-bit TPG. The circuit is based on the concept of the linear code proposed by Peterson & Welden in 1972, and Lin & Costella in 1983. In the drawing, conventional test pattern generator 100 makes use of four D-type flip-flops as shift registers. These four shift registers 11, 12, 13, and 14 are respectively provided with inputs D1, D2, D3, and D4, and four outputs Q1, Q2, Q3, and Q4 connected in a close loop. In such a way, output Q1 of first shift register 11 is connected to input D2 of second shift register 12. Output Q2 of second shift register 12 is connected to input D3 of third shift register 13. Output Q4 of fourth shift register 14 is connected to input D1 of first shift register 11. Further, outputs Q3 and Q4 of third and fourth shift registers 13 and 14 pass through exclusive-OR (XOR) gate 10 serving as input D4 of fourth shift register 14. Furthermore, all of clock terminals CK1, CK2, CK3, and CK4 thereof are coupled to clock signal CLK. In Table 1, the truth table of the sequences associated with outputs Q1, Q2, Q3, and Q4, in response to the clock signal CLK, are listed.
TABLE 1 ______________________________________ CLK Q1 Q2 Q3 Q4 ______________________________________ 1 1 0 0 0 2 0 1 0 0 3 0 0 1 0 4 0 0 0 1 5 1 0 0 1 6 1 1 0 1 7 1 1 1 1 8 1 1 1 0 9 0 1 1 1 10 1 0 1 0 11 0 1 0 1 12 1 0 1 1 13 1 1 0 0 14 0 1 1 0 15 0 0 1 1 16 1 0 0 0 ______________________________________
Initially, assuming that (Q1,Q2,Q3,Q4) is (1,0,0,0), the test pattern appears at the outputs Q1, Q2, Q3, and Q4 in the sequence from the top to the bottom, in accordance with Table 1. For example, (Q1,Q2,Q3,Q4) is (1,0,0,0) in the first clock period, (Q1,Q2,Q3,Q4) is (0,1,0,0) in the second clock period, (Q1,Q2,Q3,Q4) is (1,0,0,1) in the fifth period, (Q1,Q2,Q3,Q4) is (1,0,1,0) in the tenth period, and (Q1,Q2,Q3,Q4) is (0,0,1,1) in the fifteenth period, and so on. Notice should be taken that the test pattern starts to recur again after fifteen clock CLK periods, namely, that (Q1,Q2,Q3,Q4) is (1,0,0,0) once again. In other words, the circuit, shown in FIG. 1, accomplishes 15 separate test patterns during 15 CLK periods. For a 4-bit circuit, Table 1 consists of nearly all possible faults of a sequential digital integrated circuit except for an all zeros pattern, (0,0,0,0). However, when falling into a pattern of all zeros, which can occur after power on/reset or result from external radiation interference, the test pattern generator will sink into a self-looping mode because of the XOR gate operation. Therefore, the TPG 100 will not follow the sequence depicted in Table. 1 and the testing thereof is failed. Moreover, the conventional test pattern generator can not achieve 100% fault coverage because of being prohibited from operating properly with the pattern of all zeros. Accordingly, the conventional test pattern generator of the prior art isn't an exhaustive test pattern generator, but merely a pseudo-exhaustive one.